----------------------------------------------- EURASIP Journal on Applied Signal Processing ----------------------------------------------- Special Issue on Signal Processing for Broadband Access Systems: Techniques and Implementations With the rapid growth of Internet access and voice/data-centric communications, many access technologies have been developed to meet the stringent demand of high-speed data transmission and bridge the wide bandwidth gap between ever-increasing high-data-rate core networks and bandwidth-hungry end-user networks. To make efficient utilization of the limited bandwidth of existing access routes and cope with the adverse channel environment, many standards have been proposed for a variety of broadband access systems over different access environments (twisted pairs, coaxial cables, optical fibers, fixed or mobile wireless). These access environments may create different channel impairments and dictate unique sets of signal processing algorithms and techniques to combat specific impairments. In the design and implementation domain of those systems, many research issues arise. Firstly, multi-standards co-exist in many access environments. In addition, multi-mode or rate-adaptive designs are encountered frequently even within one single standard. Hence, dynamically configurable platform or multi-mode transceiver architectures need to be investigated for ubiquitous access. Secondly, among all layers of the access systems, application-specific accelerator designs are desired to either enhance the computational power, or lower the burden of general-purpose MCU and DSP processors. Finally, most DSP algorithms in broadband access systems are computationally intensive in nature. With currently available processing power of DSP processors and area/speed/power/fixed-wordlength limitation of ASIC designs, some of the originally developed DSP algorithms cannot be feasibly implemented, or need to suffer from performance degradation due to the implementational constraint. Consequently, novel cost-efficient DSP techniques at the implementational level need to be developed to either meet the cost/speed/power criteria of hardware design, or help to reduce the MIPS count in running DSP processors. The design goal is to achieve the targeted transmission rate under feasible implementational vehicles (FPGA, SOPC, SOC, etc.) in attempt to maintain the desired SNR performance. The aim of this special issue is to present state-of-the-art signal processing techniques and implementation issues for broadband access systems over different access channels. We solicit high quality and original works on the design, implementation, and application aspects of current and emerging wireline/wireless access technologies, such as xDSL, Cable modem, FTTC, FTTH, 10G/Gigabit Ethernet, Bluetooth, Wireless LAN, Broadband Wireless Access, Digital Audio/Video Broadcasting, etc. Topics of interest include (but are not limited to): - Cost-efficient algorithms for estimation, detection, synchronization, and equalization - Parallel DSP architectures and algorithms for high-data-rate transmission - Dynamically reconfigurable and scalable datapath units - Rate-adaptive and MIPS-on-demand DSP algorithms - Intelligent analog signal processing for communication systems - DSP compensation techniques for channel impairments under different access environments - Low power and high speed custom design and implementation of DSP algorithms - Numerically stable DSP algorithms and architectures for fixed-point implementations - Functional-specific DSP accelerator designs - Multi-mode transmitter and receiver architectural designs - Reconfigurable communications processor designs - Hardware-software co-design for broadband access communications - DSP techniques for optical communications Authors should follow the EURASIP JASP manuscript format described at the journal site http://asp.hindawi.com/. Prospective authors should submit an electronic copy of their complete manuscript through the EURASIP JASP's web submission system at http://asp.hindawi.com/wss/, according to the following timetable. Manuscript Due January 31, 2003 Acceptance Notification July 31, 2003 Final Manuscript Due September 30, 2003 Publication Date 1st Quarter, 2004 GUEST EDITORS: Prof. An-Yeu (Andy) Wu, Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan; andywu@cc.ee.ntu.edu.tw Dr. Ut-Va Koc, Bell Labs, Lucent Technologies Murray Hill, NJ 07974, USA; koc@lucent.com Prof. Keshab K. Parhi, Department of Electrical and Computer Engineering, University of Minnesota Minneapolis, MN 55455, USA; parhi@ece.umn.edu